From The Next Platform, August 8:
Designing Custom Chips In-House Is The New Normal
Cloud giants Amazon, Alibaba, Baidu, Facebook, Google, and Microsoft are now designing their own AI accelerator chips. Is this a fad or a short-term phase the cloud industry is going through? We believe that designing custom chips for specific tasks will become mainstream, in and out of the cloud. Few chip market segments will be immune. Processors, network switches, AI accelerators – all will be profoundly affected.
Chip design and manufacturing is being disrupted by a new set of technical and economic enablers. Cloud giants designing AI chips is just the tip of a mass-customization asteroid impacting the computer chip manufacturing supply chain. There isn’t a single cause for this impact, there are many factors colliding at the same time:
Death Of Moore’s Law
- Death of Moore’s Law leaves us with fast, large transistor count chips, even in mature previous-generation processes
- New architecture directions based on multi-chip modules (MCM) and system-in-package (SIP)
- Chip design tools maturing into complete development tool chains
- Licensable intellectual property (IP) blocks make it easy to assemble chips
- Multi-Project Wafers (MPW) democratize fab capacity for prototyping and limited production
- Customers writing in-house software frameworks
- Web giants create scale; emerging IoT giants aggregate into scale
Moore’s law is effectively dead. Semiconductor fabrication companies (fabs) will say otherwise. However, we are at a point in the fab maturity cycle where shrinking our current transistor processes means that transistors become more unreliable and burn more power. As transistors shrink, designers must now use extra transistors to verify that a block of logic is producing correct results. And if designers pack too much logic too closely on a chip, both supplying power and dissipating the resulting heat become a challenge.
The net result is that while transistor counts are exploding at the leading edge of performance, that explosion is producing bigger, hotter chips, but the logic isn’t going to get much faster. At the same time, older fab processes, such as 28 nanometers, are still very useful for an increasing number of applications.
New Architectural Directions
If a chip designer decides not to push semiconductor technology in favor of pursuing architectural performance, then it can step back a silicon manufacturing generation or two, or simply aim for a not very aggressive chip design point in a current process. The result can be smaller, cooler, more affordable chips. Aiming for architectural advantage is the new silicon design “high ground” to get ahead of competition.
For example, Intel’s “Skylake” Xeon Scalable server processor uses about 690 mm2 of its 14 nm silicon area for high-end 28-core server processor designs. While Intel stopped quoting transistor counts, Nvida’s Volta generation of GPU chips has 21 billion transistors in Taiwan Semiconductor Manufacturing Corp’s 12 nanometer process for a reticle and yield busting 815 mm2 chip.
AMD took a different approach with its Epyc server product line. Epyc is based on AMD’s eight-core Zeppelin die. Each Epyc processor package contains four Zeppelin die connected by AMD’s proprietary Infinity Fabric on-chip interconnect, for a potential total of 32 cores using 19.2 billion transistors and 852 mm2 of silicon area. AMD’s innovative Epyc architecture is the result of different architecture and design trade-offs and uses a different mix of interconnect, logic and storage than other processor designs. The result is Epyc’s total transistor count and die area are in the same ballpark as the largest chips from Intel and Nvidia, but at much lower manufacturing cost structure. AMD hints that its architecture has the potential to scale within a single package to larger chips, larger chip counts or both.
Chip Design Tools Maturing
eSilicon, Cadence, Mentor, Synopsys and others offer cloud-hosted design platforms, virtual prototyping and verification services for chip designers with large or small budgets. While designing chips is not yet as accessible as designing web pages, the key to effectively leveraging billion-transistor design budgets is to license and/or reuse IP blocks – parallel use of repeatable structures is the key to success....MUCH MORE
