The last decade, and few years in particular, have brought a bevy of new architectures to bear for a market keen to understand what comes after Moore’s Law. From established technologies like neuromorphic and quantum devices to more recent deep learning, graph, and memory processors there is no question there are new options, but what is not clear is how to evaluate them against each other or traditional devices.
This problem is at the heart of a recent project within Georgia Tech’s Center for Research into Novel Computing Hierarchies. In 2017, researchers from the group created a testbed for emerging architectures humorously called the “Rogue’s Gallery” of chips and systems that are off the map in terms of past architectural trends. The goal is to evaluate new architectures with an eye on how new designs might penetrate the market and specifically how networking, scheduling, tooling, and other aspects will work.
The Rogues Gallery makes cutting-edge hardware available to a wide variety of researchers and application developers. Examples of such cutting-edge hardware include Emu Technology’s Chick, FPGA-based memory-centric platforms, Field Programmable Analog Devices (FPAAs), and others. Even companies like Intel and IBM are investigating novel hardware, Loihi and TrueNorth respectively.
Accelerators like GPUs have created a pronounced shift in HPC and machine learning, but there is a wide variety of possible architectural choices for the post-Moore era, including memory-centric, neuromorphic, quantum, and reversible computing. These revolutionary research fields combined with alternative materials-based approaches to silicon-based hardware have given us a bewildering array of options and “rogue devices” for the coming post-Moore era but little guidance on how to evaluate potential hardware for tomorrow’s application needs.A testbed with novel architectures sounds like fun but there are some real challenges, particularly in budget-constrained research computing. One of the finer balancing acts the team has to consider is how to invest in understand new “rogues” without overcommitting resources since not everything they evaluate will be adopted by the market. Using new hardware via containers or cloud is a key part of keeping costs low although some vendors have contributed their hardware to the cause.
As the team notes, “not all rogues become long-term products. Some fade away within a few years (or be acquired by companies that fail to productize the technology). The overall infrastructure of a testbed focused on rogues must minimize up-front investment to limit the cost of “just trying it out” with new technology. As these early-access and prototype platforms change, the infrastructure must also adapt.” Finding the limits for technologies is part of the mission and as one might imagine, that insight from Georgia Tech researchers will be of great value to startup vendors in particular.
On hand at the Rogue’s Gallery is the EMU Chick, a desktop tower implementation of the Emu architecture. The Emu design focuses on migratory threads and memory side-processing architecture combined with a high-speed Rapid IO network. It comes with EMU build VM for compiling and simulating code. The EMU Chick has 8 EMU “nodes” and EMU compiler and simulator tools
Not all of the hardware the team explores is strictly experimental. For instance, current evaluations include:
Tools: Intel FPGA SDK 2017 (17.1), Xilinx Vivado 16.3 and Xilinx SDAccel
- Nallatech 385-A – Arria 10 board available for High-level synthesis with OpenCL
- Nallatech 385-SoC– Arria 10 board that supports HDL and embedded ARM core
- Intel Arria10 DevKit
- Coming Soon: Nallatech 520N (Stratix 10)
- Xilinx MpSOC board
- Micron EX700 with AC-510 HMC + FPGA module (sponsored in part by Micron donation)
...MORE
And more chips tomorrow,
