From SemiAnalysis, February 6:
Prices are doubling again, Supercycle is bigger, and could last longer than you think
Prices of memory are going crazy. SemiAnalysis has been calling this out for over a year since late 2024. The scariest thing is that we aren't even close to the peak. We go through fab by fab production and expansion versus detailed end market demand by memory type to forecast memory revenue, pricing, and margin better than anyone else. This has all been detailed in the SemiAnalysis memory model for a while, but we will share it more publicly today. First some background.
The Inevitability of Memory Cycles: A History of Booms and Busts
Since its commercial introduction in the 1970s, DRAM has benefited from the two scaling laws that defined the semiconductor industry: Moore’s Law and Dennard scaling. The 1T1C DRAM cell, with one access transistor and one storage capacitor, scaled for decades. Shrinking transistors reduced cost per bit, while clever capacitor engineering preserved sufficient charge to maintain signal integrity.For much of the industry’s history, DRAM density scaled faster than logic, doubling roughly every 18 months instead of 24 months and driving dramatic cost reductions. As a commoditized product, manufacturers needed to sustain cost-per-bit declines to stay competitive. Suppliers who couldn’t compete on cost fell into a downward spiral: low sales left them short on cash to finance next-generation nodes, which in turn left them further behind on cost-per-bit. Many DRAM producers fell victim and went into bankruptcy, resulting in consolidation to just a few major players today.
For more details on the industry and DRAM basics, check out our technical deep dive:
The Memory Wall: Past, Present, and Future of DRAM
September 2, 2024Yet DRAM scaling has slowed significantly over the past few decades, and density gains over time have shrunk. Over the past decade, DRAM density has increased by only ~2× in total, versus roughly ~100× per decade during the industry’s peak scaling era. Capacitors are now extreme three-dimensional structures with aspect ratios approaching 100:1, storing just tens of thousands of electrons. For comparison, a small static shock when you touch a metal doorknob might involve the transfer of billions of electrons. The static charge on just a speck of dust might be 10,000x what is stored in a modern DRAM cell.
Bitlines and sense amplifiers, once secondary concerns, are now dominant constraints. Every incremental shrink reduces signal margin, increases variability, and raises cost.
Source: Micron
An easy way to understand the technical challenge in DRAM scaling is to think of a DRAM cell as a tiny bucket that holds electricity instead of water. Each bucket stores a bit of data by holding a small electrical charge. Over the years, engineers made these buckets smaller to fit more memory on a chip. At first this worked well. But today, those buckets are not just tall they are tall and narrow, each is like a tiny drinking straw standing upright. Because of the size each bucket now holds very very few electrons.
This is a problem. When the system tries to read the data, it has to detect this very faint electrical signal and distinguish it from noise. The wires that connect these cells (the “bitline”) and the tiny sensors that read them (called sense amplifiers) are now the main bottleneck. The signal is so weak that even small variations in manufacturing or temperature can cause errors.
Source: SemiAnalysis Memory Model - Sales@SemiAnalysis.com
Together, these constraints explain why DRAM density has stagnated and why DRAM scaling has slowed down significantly over the years. The collapse of DRAM scaling has far-reaching consequences across cost, architecture, and industry structure.
As density gains slow, cost per bit reductions have slowed down. DRAM pricing is now more dependent on capacity additions and cyclical supply-demand dynamics rather than technology-driven cost reductions which have been a powerful deflationary force.
Memory Cycle Part II: Key Features of a Cycle
The memory industry has been defined by commoditization, which comes with cyclicality. This outcome reflects a combination of industry-wide competitive behavior, recurring lapses in capital discipline, and the nature of DRAM scaling we explained earlier.At its core, memory’s cyclicality is driven by timing mismatches between demand changes and corresponding supply responses. Aside from the buffer of short-term inventories, DRAM supply is not very flexible. It can take years to bring meaningful new DRAM supply online, trying to meet demand that fluctuates daily.
Memory manufacturing, much like logic, is among the most capital-intensive industries in the world. Building leading-edge DRAM and NAND fabs requires multi-billion-dollar investments (which have steadily increased over the past few decades), multi-year construction timelines, extended yield-learning curves across successive process nodes, and lengthy ramp-up periods before meaningful volume production is achieved....
....MUCH MORE
Previously from SemiAnalysis:
October 8, 2024 - Chips and Data Centers: "AI Neocloud Playbook and Anatomy"
February 7 2025 - SemiAnalysis: "DeepSeek Debates: Chinese Leadership On Cost, True Training Cost, Closed Model Margin Impacts"
March 29 - "America Is Missing The New Labor Economy – Robotics Part 1"
July 13 - ZuckAI: "Meta Superintelligence – Leadership Compute, Talent, and Data" (META)
September 22 - Elon Musk's "xAI’s Colossus 2 – First Gigawatt Datacenter In The World, Unique RL Methodology, Capital Raise"
November 14 - "Microsoft's AI Strategy Deconstructed - From Energy to Tokens" (MSFT)
December 14 - Chips: "AWS Trainium3 Deep Dive | A Potential Challenger Approaching" (AMZN; NVDA)
January 4, 2026 - Electricity: "How AI Labs Are Solving the Power Crisis: The Onsite Gas Deep Dive"
